1. Field of the Invention
The invention relates to a phase locked loop (PLL) suited for portable electronic devices and more specifically to a differential voltage-controlled delay circuit usable in a differential voltage-controlled oscillator for use in such PLLs.
2. Description of the Prior Art
Ring oscillators have come to attract engineer""s attentions as the voltage-controlled oscillator (VCO) for use in PLLs. This is because ring oscillators have a wider oscillation range covering a GHz order and are suitable for monolithic integration, which enables a reduction in the size of integrated circuit (IC) chip.
As the degree of integration becomes higher, IC patterns are further miniaturized, which lowers the withstand voltages of circuit elements constituting the IC. For this reason, desired is ring oscillators and PLLs that can operate with a lower power supply voltage. Also, in order that ring oscillators or PLLs can be used in portable electronic devices, which are usually provided with a lower power battery, it is preferable that ring oscillators are low in power consumption.
FIG. 1 is a circuit diagram showing an exemplary arrangement of a typical voltage-controlled ring oscillator disclosed in U.S. Pat. No. 5,418,499. In FIG. 1, the ring oscillator 102 is constituted by connecting an odd number of (3 in this specific example) variable-delay inverters 120-1, 120-2 and 120-3 in the form of a ring. Each variable-delay inverter 120-i (i=1, 2, 3) comprises p-channel MOS FETs (metal oxide semiconductor field-effect transistors) (referred to as xe2x80x9cpMOS transistorsxe2x80x9d) TP2 and TP1 and n-channel MOS FETs (referred to as xe2x80x9cnMOS transistorsxe2x80x9d) TN1 and TN2 serially-connected (so-called totem pole-connected) between a power supply line L1 and a ground line L2.
The pMOS transistor TP1 and the nMOS transistor TN1 of which the gates and the drains are connected together to form a CMOS (complementary MOS) inverter are referred to as xe2x80x9cswitch elements TP1 and TN1xe2x80x9d, respectively. The pMOS transistor TP2 and the nMOS transistor TN2 are referred to as xe2x80x9ccurrent-control elements TP2 and TN2xe2x80x9d, respectively.
The input and output terminals of the CMOS inverter comprised of the switch elements TP1 and TN1 serve as the input and the output terminals of each variable-delay inverter 120-i. A first control voltage Vc1 is applied in common to the current-control element TP2 of each inverter 120-i, and a second control voltage Vc2 is applied in common to the current-control element TN2 of each inverter 120-i. 
FIG. 2 is a diagram showing an equivalent circuit of a variable-delay inverter 120-i to illustrating the operational principle of the voltage-controlled ring oscillator 102. In FIG. 2, the equivalent circuit comprises a one-stage variable-delay inverter 120-i and an equivalent capacitor Cin inserted between the output terminal Vo of the inverter 120-i and the ground line VG and equivalent to the input capacitance of the next stage variable-delay inverter 120.
First, it is assumed that the two current-control elements TP2 and TN2 are completely on having the ground voltage VG applied as the first control voltage Vc1 and the power voltage VD applied as the second control voltage Vc2. Then, if the input Vi of the variable-delay inverter 120 is high or at the power supply voltage VD, the switch element TP1 is off and the switch element TN1 are on resulting in the output of the variable-delay inverter 120 being low or at the ground voltage VG.
In this state, if the input voltage Vi changes from the high level to the low level, then the switch element TP1 turning on and the switch element TN1 turning off causes the equivalent capacitor Cin to be charged through the current-control element TP2 and the switch element TP1, which results in the high level of the output voltage Vo. The charge current in this case is controlled by the current-control element TP2 and the first control voltage Vc1.
In this state, if the input voltage Vi changes from the low level to the high level, then the switch element TP1 turning off and the switch element TN1 turning on causes the equivalent capacitor Cin to be discharged through the switch element TN1 and the current-control element TN2, which results in the low level of the output voltage Vo. The discharge current in this case is controlled by the current-control element TN2 and the second control voltage Vc2.
More specifically, as shown in FIG. 3, if the input voltage Vi changes from the high level to the low level at time t1, then, with a certain delay after the input voltage Vi change, the output voltage Vo begins to change (rise in this case) at time t2. In this case, the larger the first control voltage Vc1 is, the smaller the gate-source voltage of the current-control element TP2, resulting in a smaller charging current. Thus, as the first control voltage Vc1 increases in magnitude, the change in the output voltage Vo or the waveform of voltage across the equivalent capacitor Cin varies as shown by waveforms labeled xe2x80x9caxe2x80x9d, xe2x80x9cbxe2x80x9d and xe2x80x9ccxe2x80x9d.
Similarly, if the input voltage Vi changes from the low level to the high level at time t3, then, with a certain delay after the input voltage Vi change, the output voltage Vo begins to change (fall in this case) at time t4. In this case, the smaller the second control voltage Vc2 is, the smaller the gate-source voltage of the current-control element TN2, resulting in a smaller charging current. Thus, as the second control voltage Vc2 decreases in magnitude, the change in the output voltage Vo or the waveform of voltage across the equivalent capacitor Cin varies as shown by waveforms labeled xe2x80x9cdxe2x80x9d, xe2x80x9cexe2x80x9d and xe2x80x9cfxe2x80x9d.
That is, with a larger first control voltage Vc1 and/or a smaller second control voltage Vc2, it takes the longer delay time for the output voltage to reach a threshold level to turn to the inverted level after the inversion of the input voltage Vi level.
Thus, in each variable-delay inverter 120-i, the rising characteristic of the output voltage Vo varies depending on the first control voltage Vc1, and the falling characteristic of the output voltage Vo varies depending on the second control voltage Vc2, which causes a change in the propagation delay of each variable-delay inverter 120-i and accordingly in the oscillation frequency of the ring oscillator 102.
However, in the above-described voltage-controlled ring oscillator 102, a lowering of the power supply voltage VD decreases the charging and discharging currents that flow during a period of inversion of the output voltage, which lowers the oscillation frequency. If the power supply voltage VD becomes too low to keep the gate-source voltages at a level necessary for turning on the switch elements TP1 and TN1 and the current-control elements TP2 and TN2, then the voltage-controlled ring oscillator 102 ceases oscillation.
Also, in the above-described ring oscillator 102, which includes four serially connected transistors, two of the four transistors have to be turned on at a time. In order to maintain an enough gate-source voltage, the power supply voltage cannot be lowered so much.
One of the solutions to this problem is provided by Japanese unexamined patent publication No. Hei10-200382 entitled xe2x80x9cVoltage Controlled Oscillator Circuit for Low Voltage Drivingxe2x80x9d. This voltage controlled oscillator circuit comprises a ring oscillator portion consisting of three 2-transistor inverters and an oscillation frequency controller for providing a power supply voltage to the ring oscillator portion. That is, the oscillation frequency is controlled by controlling the power supply voltage to the ring oscillator portion. Since the parasitic capacitance of the MOS FET gate is on the order of several to tens fF (femtofarad), if it is assumed that the gate capacitance is 10 fF, the oscillation frequency controller output (i.e., the power supply voltage to the ring oscillator portion) is 1.8 V and the oscillation frequency is 500 MHz, then the gate current of each transistor is 10 (fF)xc3x97500xc2x7106 (Hz)xc3x971.8 (V)=9 xcexcA, which means that each inverter needs a current of mA order. In order to provide a stable power supply voltage while supplying a current (more than mA order) enough to drive the ring oscillator portion, the oscillation frequency controller has to keep the inner current level more than a predetermined value. Thus, though the voltage controlled oscillator circuit enables the low voltage driving, it is not effective in reduction of the power consumption.
Also, to the problem of lowering the power supply voltage while securing the necessary gate-source voltage, it is another solution to set the threshold value of the MOS FETs constituting the ring oscillator 102 to a lower value. However, in the MOS FET, if the threshold value were set lower, then the leak current would increase in magnitude. This makes it difficult to reduce the power consumption.
What is needed is a voltage-controlled ring oscillator which is relatively small in a lowering of oscillation frequency due to the lowering of the power supply voltage and which can operate with a lower power supply voltage without increasing the leak current of the constituent MOS FETs.
What is needed is a PLL, a clock recovery circuit and a frequency synthesizer that use a voltage-controlled ring oscillator which is relatively small in a lowering of oscillation frequency due to the lowering of the power supply voltage and which can operate with a lower power supply voltage without increasing the leak current of the constituent MOS FETs.
According to an aspect of the invention, a variable delay circuit for providing a delayed version of an input signal is provided. The variable delay circuit is preferably connected to an input of a load which input has a capacitance. The variable delay circuit comprises an input terminal to which the input signal is applied; an output terminal to be connected to the input of the load; first and second control terminals to which first and second control signals that determine the amount of delay are applied; and a switching circuit. The switching circuit includes a first switching element comprising a p-channel MOS transistor having its drain connected to the output terminal and its source connected to a higher power supply conductor; and a second switching element comprising an n-channel MOS transistor having its drain connected to the output terminal and its source connected to a lower power supply conductor. The variable delay circuit further includes an off control circuit, responsive to the input signal, for turning off one of the first and second switching elements by shorting a gate-source path of the one switching element; and a current control circuit, responsive to an off state of the second switching element, for causing the first control signal to control a first current flowing through the first switching element by providing a conductive path between the first control terminal and a gate of the first switching element, and responsive to an off state of the first switching element, for causing the second control signal to control a second current flowing through the second switching element by providing a conductive path between the second control terminal and a gate of the second switching element.
According to another aspect of the invention, an integrated circuit including the load and the above-described variable delay circuit is provided. The load and the variable delay circuit are disposed along a first direction. Along the first direction, there are disposed: a first block in which the first off control element and the first current control element are disposed along a second direction perpendicular to the first direction; and a second block in which the second off control element and the second current control element are disposed along the second direction. The first and second switching elements are disposed in respective areas, lying along the second direction, between which the first block and the second block are disposed.
According to further aspect of the invention, a voltage-controlled ring oscillator using the above-described variable delay circuit is provided. The voltage-controlled ring oscillator includes an odd number of inverter circuits as the load. The output of the load is connected to the input terminal. The voltage-controlled ring oscillator oscillates at a frequency responsive to the first and second control signals.
According to further aspect of the invention, a phase locked loop (PLL) circuit using the above-described voltage-controlled ring oscillator is provided. The PLL circuit includes a control circuit for generating the first and second control signals on the basis of a phase difference between a reference signal given from external and a divide-by-N signal into which an output signal from the voltage-controlled ring oscillator is divided by N, where N is an integer including 1.